Multi-thread program with FreeRTOS, based on Producer /Consumer Architecture with queues synchronizing data between threads;

The 2 producers read the ADC port for value of temperature (NTC Thermistor) and potentiometer, then send data via a queue to the consumer that convert it to degree and display it to the LCD and LEDs.


Code :

Digital thermostat Report



Stereo Vision Project

Posted: February 6, 2016 in Uncategorized

Servo-actuated stereo vision project with Visual studio C++ and OPENCV. Objective track object and give the depth in cm. Using Polulu servo controller to steer the Hitec digital servos and Turnigy 2S Lipo to power it all. Baseline between cameras == 11cm. Algorithm steps are:

  1. Offline calibration
  2. Undistort images
  3. Rectify images
  4. Find features (Camshit or HSV color Filter + Blob detection)
  5. Triangulation

Link:  Technical Report Vision Project

This slideshow requires JavaScript.



Testing Camshift :

GPS Project

Posted: January 17, 2016 in Uncategorized

Based on least square method to solve GPS receiver position from raw data of a GPS device, we follow this algorithm :



Choose a starting user position. (Latitude: 45.49| Longitude: -73.56 | Altitude: 21m) (Montreal)

Choose an initial receiver clock bias cbu (cbu=0)

Iteration 1:

  1. Compute SV position in ECEF based on ephemeris data
  2. Correct SV position due to earth rotation by applying a rotation matrix to the SV pos calculated above
  3. Compute the Azimuth and Elevation of the SV used below in ionosphere and troposphere algo.
  4. Correct the pseudoranges by calculating:
    1. SV clock bias using the algorithm described in project appendix
    2. Ionosphere clock bias using the algorithm described in project appendix
    3. Troposphere clock bias using the algorithm described in project appendix
  5. Compute a coarse estimate to the receiver position [X Y Z] in ECEF and Receiver clock bias Cbu based on the assumptions of transit time tau and intial user position guess. (Least square method).

Iteration 2:

  1. New Receiver time: Ttrc = Ttrc + (Cbu/c)
  2. New Transit time: tau= (pseudorange+ cbu)/c
  3. Update GPS transmission time: Ttr= Ttrc -tau
  4. Re do step 1 to 5 with the newly corrected Ttr and tau to obtain a finer estimate of the user position

Note: The solution converge after doing iteration 2 with more precise measurements, increasing the number of iterations do not have any effect since the solution converged from iteration 2.

GPS sv location

Satellite vehicule (Azimuth and Elevation) related to user position in center of the circle. In our case 6 Satellites are visible

The best solution is to select an optimal set of the tracked Satellite vehicule (SV) to minimize a desired DOP factor.

  • With all our 6 SV we have the following DOP factors:
4.63 3.33 1.93 3.85

Generally GDOP factor range from 2 to 3 depending on SV geometry but it can be larger than 3 especially in condition where there is not a clear view of the sky down to the Horizon. This seems to be our case.


More details are in the article by Sam van Leeuwen (GPS Point Position Calculation).

and (Farrell, Jay. Aided navigation: GPS with high rate sensors. McGraw-Hill, Inc., 2008) Chap 8.


Testbench for Multirotor

Posted: August 10, 2015 in Uncategorized


TestBench Diagram

This slideshow requires JavaScript.



This slideshow requires JavaScript.

This is the board after hand soldering.

Description of the system:

First an FT232HL received data from Java Application via USB and the sends it to the FPGA (Xilinx Spartan 6 LX9) in Asynchronous FIFO mode , the FPGA store the data in the RAM(ipcore) and then sends the 12bit data clocked @ 250MHZ (DCM ipcore) which is our max Freq achievable without distortion to the signals, to 12bit DAC (ISL5857 ) configured in complementary current output . It is connected to a THS4304 AOP that convert the differential current signals to a voltage in the +-500mV range. This signal is then filtred with a 4th order passive low pass Butterworth filter.

Mixed signal PCB design consisting of a 12 bit DAC generating a Sine wave with 0.5v Vpp.

Sampling data is acquired from PC app through USB passed to FT232HL then to the Xilinx Spatan 6 FPGA (LX9).

Data bus and clock signal are then sent to a 12 bit DAC from internstil in differential mode for better harmonic rejection. The current is enter a differential AOP and is converted to analog voltage with 500mv VPP.  At the end the signal is filtred by a 4th Order Passive Butterworth LP.

PCB was designed with matching Impedance  50 Ohm and Signal Integrity in mind to account for the high frequency critical signals paths.

Also keep digital signal away from the Analog part of the circuit and keep decoupling cap near IC.

Now we have to start coding in VHDL to bring to life

  • the DCM that will generate the DAC CLK .
  • The UART communication between the FPGA and the FTDI ( Config in FIFO Asynchronous Mode)
  • Code Optimization to run as fast as possible

    This slideshow requires JavaScript.